A processor can tick along doing its job based on a single clock, and that clock can generally be sped up or slowed down with no important changes in the function of the design. On top of that, FPGAs are doing their work in a fine-grained, highly-parallel environment. This important difference gives rise to a multitude of problems.
#PROPRIETARY FPGA SIMULATION TOOLS SOFTWARE#
While the output of a software compiler is essentially an ordered list of instructions, the output of an FPGA implementation tool is a complex physical arrangement of components and interconnect.
To be specific, FPGAs are made up of look-up-tables (LUTs), and “other stuff.” The “other stuff” includes hardened cells for doing arithmetic (multiply, accumulate, etc for digital signal processing applications), memory in various sizes, widths, and configurations, various types of IO, and sometimes even processors and peripherals. And simply changing the number or arrangement of components has a dramatic impact on the upstream tool chain. There is a complex physical array of components, whose behavior depends not only on their logical structure but also on their physical location. In the FPGA world, there is no hypervisor. With the proliferation of hypervisors and the like, it takes very little to connect higher levels of software abstraction to the bare-metal logic of the processor. These days, in fact, you don’t really even need the instruction set. If you can make a compiler, you can build an entire development suite on top of it. If you know the instruction set, you can make a compiler. Processors, by and large, can be well characterized by their instruction set. Furthermore, just gathering all the data into a form that would be useful to tool developers is a monumental task.īut, beyond the finger pointing, there are formidable technical barriers to the creation of a viable third-party ecosystem.įirst, an FPGA is not a microprocessor. They have hard-earned intellectual property that they don’t want to expose to the world, and a very rich level of detail is required for a typical design tool to do its job.
Regarding the proprietary information, there is a fine line that FPGA companies must walk in providing technical data to third-party tool developers. But FPGA companies don’t want such a huge barrier to entry for their devices, so they really do need to have a “free” tool option for designers and teams who don’t have enterprise-grade budgets. The EDA business model really requires at least five-digit price tags for a sale, although they can sometimes trim things up and get by with four-digit pricing. EDA business models would have tools selling for significant amounts of money. EDA companies were quick to blame the FPGA vendors themselves, of course, for everything from withholding important technical data, making it difficult or impossible for a third party to create working tools, to trashing the market by offering competitive tools for free. If you are looking for villains, there are plenty of options. Why is it so hard to create a viable alternative FPGA design flow? Well-minded communities have unleashed proven formulas for open-sourcing solutions to complex problems, looking for an alternative to proprietary tools. Numerous EDA companies, from fast-moving, highly-motivated, innovative startups to big lumbering institutionalized EDA vendors have poured creativity, energy, determination, and piles of cash into efforts to build a third-party ecosystem for FPGA design. It’s not that the third-party and open-source communities haven’t tried to find ways to produce viable alternative design flows. However, we are still basically at the point where there is one and only one option for doing your FPGA design – the tool suite sold and distributed by the FPGA company itself. You’d think that a technology that has been evolving and maturing for over thirty years would have long ago reached the point where there were a wide variety of competitive programming options to choose from. Wouldn’t it be great if there were more options in FPGA tools? For decades now, the FPGA community has decried the lack of FPGA design tool options.
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